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Integrated Circuit Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
FEATURES
* 2 differential HSTL compatible outputs * 1 differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL * Maximum output frequency: 700MHz * Translates any single-ended input signal to HSTL levels with resistor bias on nCLK input * Output skew: 30ps (maximum) * Part-to-part skew: 250ps (maximum) * Propagation delay: 1ns (maximum) * Output crossover Voltage: 0.68V to 0.9V * Output duty cycle: 49% - 51% up to 266.6MHz * VOH = 1.4V (maximum) * 3.3V operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85211I-01 is a low skew, high performance 1-to-2 Differential-to-HSTL Fanout Buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.The ICS85211I-01 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS85211I-01 ideal for those clock distribution applications demanding well defined performance and repeatability. For optimal performance, terminate all outputs.
,&6
BLOCK DIAGRAM
Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nCLK GND
CLK nCLK
ICS85211I-01
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
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Integrated Circuit Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Type Output Output Power Input Input Power Pullup/ Pulldown Pulldown Description Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Power supply ground. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 GND nCLK CLK VDD
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK 0 1 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0, Q1 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0, nQ1 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A JULY 16, 2003
Integrated Circuit Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VDD Outputs, VDD Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C
Symbol VDD IDD Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 22 Units V mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 150 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. HSTL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C
Symbol Parameter VOH VOL VOX VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Crossover Voltage Peak-to-Peak Output Voltage Swing Test Conditions Minimum 1.0 0 0.68 0.6 1.0 Typical Maximum 1.4 0.4 0.9 1.4 Units V V V V
NOTE 1: All outputs must be terminated with 50W to ground.
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Integrated Circuit Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Test Conditions 600MHz Minimum 0.7 Typical Maximum 700 1.0 30 250 20% to 80% 200 48 500 52 Units MHz ns ps ps ps %
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle
t sk(o) t sk(pp)
tR / tF odc
266.6MHz 49 51 % All parameters measured at 600MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JULY 16, 2003
Integrated Circuit Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V5%
V DD
Qx
SCOPE
V DD
nCLK
HSTL
nQx
V
PP
Cross Points
V
CMR
CLK
GND GND 0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
tsk(o)
DIFFERENTIAL INPUT LEVEL
Qx PART 1 nQx Qy PART 2 nQy
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK 80% Clock Outputs 80% VSW I N G 20% tR tF 20% CLK nQ0, nQ1 Q0, Q1
tPD
OUTPUT RISE/FALL TIME
nQ0, nQ1 Q0, Q1
Pulse Width t
PERIOD
PROPAGATION DELAY
odc =
t PW t PERIOD
odc & tPERIOD
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REV. A JULY 16, 2003
Integrated Circuit Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION
WIRING
THE
DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85211I-01. In this example, the input is driven by an ICS HiPerClockS HSTL driver. The decoupling capacitors should be physically located near
1.8V Zo = 50 Ohm 5 6 7 8
the power pin. For ICS85211I-01, the unused outputs need to be terminated.
Zo = 50 Ohm U1 GND nCLK CLK VDD nQ1 Q1 nQ0 Q0 4 3 2 1 Zo = 50 Ohm + R1 50 R2 50 LVHSTL Input -
Zo = 50 Ohm LVHSTL ICS HiPerClockS LVHSTL Driv er R6 50 R5 50
VDD=3.3V C1 0.1u
ICS85211-01
R3 50
Unused R4 Output 50 Need To Be Terminated
FIGURE 2. ICS85211I-01 HSTL BUFFER SCHEMATIC EXAMPLE
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Integrated Circuit Systems, Inc. CLOCK INPUT INTERFACE
The CLK /nCLK accepts differential input signals of both VSWING and VOH to meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the ICS85211I-01 clock input driven by most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
of the driver components to confirm the driver termination requirement. For example in Figure 3, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 3A. ICS85211I-01 CLK/NCLK INPUT DRIVEN HIPERCLOCKS HSTL DRIVER
BY
FIGURE 3B. ICS85211I-01 CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER (INTERFACE 1)
BY
3.3V
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK
Zo = 50 Ohm C2 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125
3.3V
R4 125
CLK
Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100-200 R6 100-200 R1 84 R2 84
nCLK
HiPerClockS Input
R5,R6 locate near the driv er pin.
FIGURE 3C. ICS85211I-01 CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER (INTERFACE 2)
BY
FIGURE 3D. ICS85211I-01 CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
BY
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REV. A JULY 16, 2003
Integrated Circuit Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85211I-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85211I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 22mA = 76.2mW Power (outputs)MAX = 82.34mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 82.34mW = 164.7mW
Total Power_MAX (3.465V, with all outputs switching) = 76.2mW + 164.7mW = 240.9mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.241W * 103.3C/W = 110C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
8-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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Integrated Circuit Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 4.
VDD
Q1
VOUT RL 50
FIGURE 4. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDD_MAX - V
L
)
OH_MAX
Pd_L = (VOL_MAX /R ) * (VDD_MAX - VOL_MAX)
Pd_H = (1.4V/50) * (3.465V - 1.4V) = 57.82mW Pd_L = (0.4V/50) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 82.34mW
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REV. A JULY 16, 2003
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ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85211I-01 is: 411
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ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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REV. A JULY 16, 2003
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ICS85211I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85211AMI-01 ICS85211AMI-01T Marking 5211AI01 5211AI01
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85211AMI-01
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LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Throughout data sheet changed LVHSTL to HSTL. Changed nCLK Type from VDD/2 to Pullup/Pulldown. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Changed RPULLUP to RPULLUP/RPULLDOWN, Pullup/Pulldown Resistors. Date
Rev
Table 1 2
Page 2 2
A
7/16/03
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